A friend sent a high-definition dieshot of Exynos9810. So I decided to draw it.
After finishing the drawing, I felt that it was quite intricate.
After completing the drawing, I realized that the units were spaced too far apart. So I made annotations.
If it's not clear, switch to dark mode.
The reason for the spacing is because the red area represents the on-chip system data bus, which connects all the modules on the chip. The CPU-GPU connection is the thickest.
There are two ways to design the bus. One is to place it on top of the existing modules, such as my 12-layer metal layer.
Layers 1-8 are for internal wiring within the module, layers 9-10 are for module interconnect buses, and layers 11-12 are for power lines. It heavily relies on the bus logic and drivers within the module.
The other option is to extend the module to the top layer and fan out the lines on the side. It's not necessarily better to have shorter lines, as higher layers have thicker metal lines with larger spacing, resulting in smaller parasitic resistance and capacitance. On the other hand, lower layers have thinner and smaller lines, leading to higher losses.
Author: kurnal
Original image: tech
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