This article is an analysis of Hi36a0V120
This article was written three days after the release of Mate60, with an unknown publication date.
Overview#
Hi36A0V120, internally codenamed Charlotte
CPU: TSV120+TSV120+A510
SUB: Self-developed bus
GPU: Maliang 910
NPU: Iterative, should still be Da Vinci NPU, 1b+1l design
Modem: No specific name, but it can be seen from the Dieshot that it has no PCIe, indicating its baseband is integrated
Manufacturing process is Smic7
Decap Analysis#
First, we are using the die provided by Gugugu, disassembled from a newly purchased Mate60Pro
It is obviously a pop package
The top package is Hynix particles
Blowing down reveals
Topmark is
Hi36A0
GFCV120
JTFQ3T0V1
2035-CN09
06
DataCode (TOP Marking) Analysis#
HiSilicon: HiSilicon Semiconductor
Hi36A0 indicates the Hi36 product line, A0 indicates the product is a tenth-generation product (123-9ABCD…)
The 1 in V120 indicates the product generation (for example, for TVs, the first generation is V100, the second generation is V200). In the Hi36 series, only Hi3690 has V100/V200, which is a dual scheme, the meaning is uncertain.
2 indicates a design GDS version change, generally optimized slowly after mass production, like hi6260v131.
0 indicates minor optimization, the rest shows no discernible pattern.
2035CN theoretically indicates the packaging date, 09 is the code for factory packaging.
The X-ray image shows it is a FanOut Package.
So, we are doing an X-ray now.
X Ray#
The X-ray clearly shows it is a FanOut Package.
The three black dots on the edge are the bump points connecting the Top Package and Bottom Package, but strangely, they are not seen in the physical image, not on the same layer of the package, possibly indicating the use of other manufacturers' flash chips later (saving the time for repackaging?).
It may also be the wiring inside the Bottom Die.
The edge clearly shows the connection bonding points between the die and the edge IO PHY, allowing for an estimated die size of approximately 10x10.
This is the data that can be seen from the X-ray image, indicating that it has been decapped.
Decap#
Decapping
After decapping, it can be seen
Its die mark appears to be HL 02 20210603, indicating it was produced on June 3, 2021.
This is a strange number because the outer package is 2035CN, while the internal actual production date is 20210603. I believe the top mark of 2035CN is a disguise, or even fixed.
No other suspected die marks were found anywhere.
Unlike previous Kirin models that used Hixxxx Vxxx version numbers, it is not directly visible.
It is impossible to determine the specific product code/version stage (for example, is it actually Hi36A0/Hi36B0?).
I believe this product belongs to an entirely new generation, rather than a simple V120 version stepping iteration, but there is not enough evidence to support my viewpoint.
Alignment System Analysis#
Three alignment systems were observed on the edge, indicating that some production line equipment is ASML's stepper lithography machine.
The marks are automatically identified through overlay measurement equipment.
Bar in Bar mark
Bar in Bar mark
AIM overlay mark
AIM overlay mark
Suspected Canon alignment system (i-line and KrF)
The most important thing is this alignment system.
In this image
You can see the regular vertical stripes, one group has 9 stripes, another group has 8 stripes, with 4 evenly spaced vertical stripes in each.
This clearly indicates that the most advanced alignment system used for this chip is
ASML's Athena alignment system.
The stripe belongs to the Versatile Scribeline Primary Mark (VSPM) AH74.
This alignment system is only used in ASML equipment.
AH74 is even rarer, available in 1960-2000i.
Now that we know the manufacturing equipment, we can calculate its capacity and yield.
Capacity Analysis#
According to known information, SMIC has about two NXT1980di machines, but has allocated 60% capacity to Huawei with an 80% utilization rate +40 DUV mask calculation.
The formula is: 550wph x 24h x 60% x 80% / 40 = 158.4 Wafer.
This die was produced in June 2021.
From then until now, it is September 1, 2023.
It is uncertain if there are earlier dies, but this is currently the earliest die, so we calculate it.
The total production time is approximately 822 days, excluding possible rest days, 800 days of production,
800 x 158.4
which is 126,720 wafers.
Yield Analysis#
Now we calculate the yield.
Internal inquiries and screen printing checks indicate that this wafer has approximately 300 dies cut.
Given the die size is 10.7x10.4, we seek yield.
Dpw can be calculated.
D0 is approximately 0.6, between 0.6-0.55, yield is 53.22%.
By the end of this year, the yield ramp-up is around 0.3.
Using a linear graph to find the midpoint, assuming uniform ramp-up.
At 400 days, D0=0.45, which means 350 good dies, yielding 61.88%.
When D0=0.3
At 800 days, D0=0.3, which means 409 good dies, yielding 72.28%.
For convenience, the median is D0=0.45.
126720 x 566 x 61.88% = 44,382,514.176
Thus, the estimated number is that Huawei produced 40-45 million Hi36a0V120 dies, roughly calculated.
Die Markings#
Searching in the die, there are several markings.
For example, the F-shaped stripes.
B+ numbers, marked areas/test points.
IO PHY
This image clearly shows the points on the edge for fan-out.
There is also a strange screen print:
2017 Mora
A?C?E?A?
A 01 0
It is unclear what this is, possibly indicating
Week 17 of 2020?
Must be 2017?
Very strange.
There is also an sa06 with a cross alignment mark on the left.
Removing the Metal Layer#
Next is the removal of the metal layer.
Since the wiring is Cu, it is acid-etched.
Acid etching will have a scrap rate, but this time it was very lucky, perfectly done.
Very beautiful, so we proceed to
Dieshot Layout#
It is clear that this chip is not the same as the Kirin 9000, it is not the same product.
I have also done the Kirin 9000.
Making a comparison.
It is evident that these two are not the same chip because the shapes of the dies are different, although their scales are similar.
This indicates that Hi36A0 V100 and Hi36A0V120 are completely different and do not belong to a rebranding or inventory.
This can fully prove that the Kirin 9000s does not belong to a similar structure as the 9000L/9000e rebranding, nor does it belong to a partially shared design structure like the 985/990.
It is an entirely new generation, with no identical parts.
So, this is the analysis of the
CPU#
First, let's compare the CPU.
You can see the huge area of the CPU cluster, which has undergone significant changes compared to the previous generation.
On the left is TSMC N5 A77+A77+A55, 134
On the right is SMIC N7 TSV120+TSV120+A510, 134
Comparison of the size of the super-large core.
The area has increased significantly.
Performance Analysis Not Written#
No L0 Cache
The architecture is too wide, requiring cache.
Regarding the small core, it is A510, with two dual-core composites at 1.53GHz, at the optimal sweet spot frequency, while under TSMC's process, it is 1.4GHz.
As for the bus in this generation, unlike the previous generation's bus and super-large core using a performance library.
In this generation, only the super-large core uses a performance library.
The color change is due to
I believe it is caused by the density of the poly layer transistors leading to changes in the reflected spectrum.
GPU Analysis#
The previous generation Mali G78 Mc24 is a typical stacked material.
Mali G78 is based on the Valhall architecture, and mc24 indicates it has 24 cores.
Its GPU is a core design, while this generation's Maliang is a CU design.
The design scale is slightly smaller than the previous generation.
The unit division is shown in the image.
It has 4 CUs, with two groups of ALU cores on each side, each group having 128 ALUs, totaling 2x4x128 ALUs = 1024 ALUs.
The maximum frequency is 750MHz, with a theoretical performance of 1536 Gflops.
The middle part is the GPU L2 Cache, approximately 1 MiByte.
From the specifications of the GPU,
it does not match common IMG/MALI/Adreno/RDNA/CUDA.
I believe this is a completely new self-developed GPU.
NPU#
In this generation of NPU,
the previous generation had dual large cores + 1 small core NPU, with each large core having two vectors.
This generation has a single large core + 1 small core NPU, with the large core having two slightly longer vectors.
From a macro perspective, I believe that although the scale has reduced by one large core, it may enhance performance due to microarchitecture updates, but the reduction in core scale is a fact, saving a significant area for other units.
ISP#
The scale of the ISP has clearly increased compared to the previous generation ISP 6.0, but the common core of these two ISPs can be found.
In the center, there seems to be a newly added dual-core co-processor.
The theoretical image processing speed has increased; this generation's Mate60 Pro can achieve HDR Vivid in the viewfinder and smooth transitions during zooming, which is a result of the increased ISP computing power.
This ISP runs at mid-frequency, 2W, which is extremely impressive.
DSP#
There is not much to say about the DSP.
It doesn't show much; compared to the previous generation's decode, it seems to have one less unit.
The area has shrunk a little.
Baseband#
In the baseband,
the design of this generation is completely different from the previous Balong 5000.
Its area has significantly reduced.
Previously, Huawei's 5G baseband was always designed as 4G + 5G, with an interconnection bridge for data transmission.
Some external basebands, such as the 990 4G, used PCIe x8+x16 for data transmission, then connected to the Balong 5000.
In this generation's modem design, it is a pure Balong Baseband Modem System, integrating 4G and 5G, allowing for shared DSP and modem, eliminating the need for separate designs.