Let's talk about Telum.
First of all, Telum is not z16, it is a new generation that shows some influence from power, but it is not entirely power.
Because Telum leans towards its banking, it requires encryption and other needs.
And the important thing to discuss is the design of the cache.
Telum has eliminated L3 and L4 and replaced them with a huge L2. This design will cause the cache to have a significant access latency. However, Telum is quite amazing. It places the data that used to be stored in L3 in the L2 of the remaining idle cores, and the same goes for L4. This means that, in a sense, a chip physically has 256M of L2 (8X32), but a single core can access the 32M L2 outside the core, 256M L3, and the entire complex (the entire IBM z16? unit) has 32mx8 cores x2 (2 dies packaged in one sub) x16, which is an 8GB L4. To put it simply, if a core's data cannot fit, it can be placed in the L2 of other cores, different substrates, or even different groups or units, as long as they are available.
This is... quite strange? But this is also the future of cache.
There is not much to discuss about other cores, as they have many vulnerabilities. Just bear with it.
4-channel DDR5 x8x4pcie5.0, a bunch of AI encryption units...
The IBM Telum Dieshot drawing, image from the IBM official website, created/drawn by Kurnal.
Reprinting instructions: The drawing is from Kurnal.